1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a trench isolating film.
2. Description of the Background Art
A semiconductor device (which will be hereinafter referred to as an SOI device) having an SOI structure formed on an SOI substrate in which a buried oxide film and an SOI (Silicon On Insulator) layer are provided on a silicon substrate can reduce a parasitic capacitance and is characterized by a quick and stable operation and low power consumption, and is thereby used for portable equipment or the like.
As an example, an SOI device has a perfect trench isolation (FTI) structure for electrically isolating elements by a perfect trench isolating film formed by providing a trench reaching a buried oxide film in a surface of an SOI layer and burying an insulating material in the trench. However, a carrier (a hole in NMOS) generated by an impact ionization phenomenon is accumulated in a channel formation region. Consequently, various problems arise by a substrate floating effect, for example, a kink is generated and an operating breakdown voltage is deteriorated, and furthermore, an electric potential of the channel formation region is not stabilized so that a frequency dependency of a delay time is generated.
Therefore, there has been devised a partial trench isolation (PTI) structure formed by providing a trench in a surface of an SOI layer to leave the SOI layer having a predetermined thickness between a bottom portion of the trench and a buried oxide film and burying an insulating material in the trench.
FIG. 74 shows a sectional structure of an MOS transistor Q10 having the PTI structure. In FIG. 74, a sectional structure in a direction of a gate width of the MOS transistor Q10 is illustrated.
As shown in FIG. 74, a partial isolating oxide film PT is provided in a surface of an SOI layer 3 of an SOI substrate constituted by a silicon substrate 1, a buried oxide film 2 and the SOI layer 3, and a gate oxide film 11 and a gate electrode 12 are sequentially provided on an active region AR defined by the partial isolating oxide film PT.
The SOI layer 3 is present between a bottom portion of the partial isolating oxide film PT and the buried oxide film 2 to form a well region WR, and a carrier can be moved through the well region WR and can be prevented from being accumulated in a channel formation region, and furthermore, an electric potential of the channel formation region can be fixed through the well region WR (body fixation). Therefore, there is an advantage that various problems do not arise by the substrate floating effect.
In the PTI structure, however, a depth of the partial isolating oxide film PT is mainly defined by etching during formation of a trench, and is also varied in the same wafer or between different wafers due to a variation in the etching.
As shown in FIG. 74, the depth of the partial isolating oxide film PT is defined as a depth d10 from a surface of a main surface of the SOI layer 3 to a bottom portion. For example, in the case in which d10=100 nm is set to be a design value, the depth of the partial isolating oxide film PT to be actually formed is set to d10=100 nm±5 nm and is varied within a range of 95 to 105 nm.
The foregoing implies that a thickness of the well region WR in a lower part of the partial isolating oxide film PT is varied within a range of 45 to 55 nm if a thickness of the SOI layer 3 is set to be approximately 150 nm. If the design value of the well region WR is set to be 50 nm, the variation is equivalent to ±10%.
The etching to be carried out when forming the trench in the partial isolating oxide film PT will be further described with reference to FIGS. 75 and 76.
As shown in FIG. 75, first of all, an SOI substrate is prepared and an oxide film 4 is formed on the SOI layer 3 of the SOI substrate.
Next, a polysilicon film 21 is formed on the oxide film 4 by a CVD (Chemical Vapor Deposition) method, and a nitride film 22 is formed on the polysilicon film 21 by the CVD method. The oxide film 4, the polysilicon film 21 and the nitride film 22 are also referred to as auxiliary films because they auxiliary function for forming an isolating oxide film.
As shown in FIG. 76, then, the nitride film 22 and the polysilicon film 21 are selectively removed by dry etching or wet etching using a resist mask (not shown) having a predetermined opening pattern.
By using the patterned nitride film 22 as an etching mask, furthermore, the oxide film 4 is penetrated and the SOI layer 3 is etched in a predetermined depth to form a trench TR. In the etching, etching conditions are adjusted such that the SOI layer 3 is not completely etched to expose the buried oxide film 2 but the SOI layer 3 having a predetermined thickness remains in a bottom portion of the trench TR.
A total amount of etching of the nitride film 22, the polysilicon film 21, the oxide film 4 and the SOI layer 3 is 200 to 400 nm. Even if a depth of a partial isolating oxide film PT is set to be small, for example, approximately 50 nm, the total amount of etching is 150 to 350 nm. Thus, the total amount of etching is not very changed. Consequently, a variation is not greatly changed.
For this reason, in the case in which a depth of the trench TR is set to be 50 nm for the SOI layer 3 having a thickness of 70 nm, the thickness of the well region WR in the lower part of the partial isolating oxide film PT is varied within a range of approximately ±5 nm. If the design value of the thickness of the well region WR is set to be 20 nm, a variation is equivalent to ±25%, which cannot be permitted. The variation is further increased with a reduction in the thickness of the SOI layer 3 so that the body fixation of the PTI structure is substantially limited. In the thin SOI layer, thus, it is hard to form a partial isolating oxide film and it is difficult to carry out the body fixation by the PTI structure.
As a method of carrying out the body fixation other than the body fixation using the PTI structure, moreover, there has been proposed such a structure that a planar shape of a gate electrode is changed or a position in which a body contact portion for the body fixation is to be formed is taken into consideration.
FIG. 77 is a planar layout of a gate electrode which is referred to as a T type gate, illustrating a gate electrode 12T in which one of ends in a direction of a gate width is greatly enlarged in a direction of a gate length to constitute a gate contact pad GP and which has a “T” shape seen on a plane.
A body contact portion BD is provided on the outside of a tip of a head portion of the “T” shape in the gate electrode 12T. An impurity region having a reverse conductivity type to that of a source-drain region is formed in a surface of the SOI layer 3 in the body contact portion BD.
Moreover, an active region AR including the source-drain region and the body contact portion BD are provided continuously.
FIG. 78 shows a structure of a section taken along a line A-A in FIG. 77. As shown in FIG. 78, in the case in which an MOS transistor has an N conductivity type, the SOI layer 3 provided under the gate electrode 12T contains a P type impurity in a comparatively low concentration (P−), while the body contact portion BD contains the P type impurity in a comparatively high concentration (P+). The active region AR and the body contact portion BD are defined by a perfect trench isolating oxide film FT.
By employing such a structure, the active region AR is defined by the perfect trench isolating oxide film FT. Therefore, a variation in the depth of the trench is not generated so that a reduction in the thickness of the SOI layer 3 has no problem. Moreover, the electric potential of the channel formation region can be fixed through the body contact portion BD so that a stable operation can be implemented.
Examples of a structure to produce the same functions and effects includes a structure referred to as an H type gate shown in FIG. 79 and a structure referred to as a source tie shown in FIG. 80.
In the H type gate shown in FIG. 79, both ends in a direction of a gate width are greatly enlarged in a direction of a gate length, and a gate electrode 12H having an H-shaped planar shape is provided and two body contact portions BD are provided.
In the source tie structure shown in FIG. 79, the band-shaped body contact portion BD is provided in a part of a source region SR and one end of the body contact portion BD is connected to a channel region provided under the gate electrode 12.
In the case in which the T type gate structure or the H type gate structure is employed, however, there is a problem in that a parasitic capacitance between a gate and a drain is increased corresponding to an increase in an area of a gate electrode and a quick and stable operation cannot be carried out.